In general, the present invention relates to a playback apparatus and a playback method. In particular, the present invention relates to a playback apparatus and a playback method for computing interpolation values of a given signal at a predetermined phase of a second clock signal as an ultimate playback signal by typically linear interpolation using first and second digital values as base points. The second digital values are found from the first digital values which are obtained by sampling the given signal at sampling times synchronized with a first clock signal. To put it in detail, the second digital values are each found by interpolation using the first digital values as base points at a time different from the sampling times at which the first digital values are found from the given signal in synchronization with the first clock signal. The interpolation is based on a function of at least a second order.
A compact disk, a representative recording medium for storing digital data, is becoming more and more popular in a wide range of applications.
When digital data is reproduced from such a recording medium like, for example, an optical disk or an opto-magnetic disk, in most cases, a clock signal is extracted from a signal detected from the disk and digital data is then reproduced from the detected signal in synchronization with the extracted clock signal. Synchronization of extracting data from a signal with a clock signal extracted from the same signal is referred to as the so-called self synchronization.
In such self synchronization, the clock signal is extracted from the detected signal by using a PLL (Phase Locked Loop) circuit.
FIG. 1 is a diagram showing a typical configuration of the conventional playback apparatus having an analog PLL circuit.
As shown in the figure, a read-out device 121 radiates a laser beam to an optical disk 201 such as a compact disk and receives a laser beam reflected by the optical disk 201, that is, a return light coming from the optical disk 201. An electrical signal representing the quantity of the incoming return light is then supplied by the read-out device 121 to a waveform shaping unit 122. The electrical signal is the so-called playback signal.
The waveform shaping unit 122 converts the playback signal supplied by the read-out device 121 into a binary signal and outputs the binary signal to a latch circuit 123 and an analog PLL circuit 124 as a playback signal.
The analog PLL circuit 124 extracts a clock signal from the playback signal supplied by the waveform shaping unit 122 and supplies the clock signal to the latch circuit 123. Values of the binary playback signal which are either 0 or 1 change at intervals each equal to a multiple of a predetermined bit period T. It should be noted that the intervals each correspond to a piece of data recorded on the optical disk 201. The analog PLL circuit 124 extracts the bit period T from the interval, generating a clock signal having a period corresponding to the bit period T.
In the analog PLL circuit 124, a phase comparator 141 computes a phase error between the playback signal supplied by the waveform shaping unit 122 and a clock signal (a PLL clock signal) oscillated by a voltage controlled oscillator (VCO) 143. The phase error is output by the phase comparator 141 to a loop filter 142 for eliminating high-frequency components, that is, components in an unnecessary frequency band, from the phase error. The loop filter 142 then outputs the processed phase error to the VCO 143.
In accordance with the voltage of a signal supplied from the loop filter 142, the VCO 143 oscillates the PLL clock signal while adjusting the frequency thereof so that the phase error with respect to the playback signal supplied by the waveform shaping unit 122 is eliminated. The PLL clock signal is fed back to the phase comparator 141 and, at the same time, supplied to the latch circuit 123.
In this way, the analog PLL circuit 124 generates the PLL clock signal synchronized with the playback signal.
The latch circuit 123 outputs the playback signal supplied by the waveform shaping circuit 122 in synchronization with the PLL clock signal oscillated by the analog PLL circuit 124 to a playback circuit at the following stage which is not shown in the figure.
However, the analog PLL circuit 124 has a problem that it is easily affected by changes in environment, changes with the lapse of time and component variations. There is also raised a problem that it is difficult to put the analog PLL circuit in a highly integrated circuit chip due to the fact that the PLL circuit is an analog circuit.
In order to solve the problem, a digital PLL circuit has been developed.
FIG. 2 is a diagram showing a typical configuration of a digital PLL circuit.
As shown in the figure, the digital PLL circuit comprises a digital phase comparator 161, a digital loop filter 162 and a variable-frequency oscillator (VFO) 163 as a substitute for the VCO. The VFO 163 adjusts the frequency of an output signal thereof by adding or eliminating pulses to and from the output signal in accordance with the digital value of a phase error supplied by the digital phase comparator 161 to the VFO 163 by way of the digital loop filter 162. As an alternative, including two embedded oscillators with frequencies different from each other, the VFO 163 adjusts the frequency of an output signal thereof by switching the generation of the output signal from on e embedded oscillator to the other embedded one in accordance with the digital value of a phase error supplied by the digital phase comparator 161 to the VFO 163 by way of the digital loop filter 162.
In order to adjust the oscillation frequency smoothly in accordance with phase error, the VFO 163 generates an interim output signal with a frequency equal to a multiple of the frequency of a finally desired clock signal by adjusting the frequency of the interim output signal. The VFO 163 supplies the interim output signal to a frequency divider 164 for dividing the frequency thereof. The output of the frequency divider 164 is the finally desired clock signal which is fed back to the digital phase comparator 161 and, at the same time, supplied to a circuit at the following stage which is not shown in the figure.
In an apparatus for processing data at a high speed or in an apparatus having a high transfer speed, by the way, the frequency of the clock signal used in the apparatus is high. There is thus raised a problem that it is difficult to implement a VFO which is capable of oscillating an interim output signal with a frequency equal to a multiple of the high frequency of the clock signal and that, even if such a VFO can be implemented, the cost thereof will be high.
In order to solve the problem described above, the applicant of the application of the present invention for a patent disclosed an apparatus capable of operating at a relatively low frequency in documents such as Japanese Patent Laid-open No. Hei8-184428 wherein a second clock signal is generated in synchronization with a first clock signal while adjusting the clock frequency of the second clock signal in accordance with a phase error of a playback signal and an interpolation value at a predetermined phase of the second clock signal is computed from sampled values (referred to as first digital values) obtained by sampling the playback signal in synchronization with a first clock signal while adjusting the clock frequency of the second clock signal as shown in FIG. 3.
This apparatus includes an interpolation circuit, a circuit for computing an interpolation value at a predetermined phase of the second clock signal, as a configuration element of the PLL. Thus, in order to carry out PLL processing at a high speed, that is, in order to guarantee a good loop characteristic over a wide of range, a simple computing technique such as linear interpolation is adopted to compute interpolation values of the playback signal.
With a simple computing technique such as linear interpolation, however, errors are generated in the resulting data due to interpolation errors, giving rise to a problem that it is difficult to reduce the data-error rate.